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CMOS STATIC RAM 256K (32K x 8-BIT)
Integrated Device Technology, Inc.
IDT71256S IDT71256L
FEATURES:
* High-speed address/chip select time -- Military: 25/30/35/45/55/70/85/100/120/150ns (max.) -- Commercial: 20/25/35/45ns (max.) Low Power only. * Low-power operation * Battery Backup operation -- 2V data retention * Produced with advanced high-performance CMOS technology * Input and output directly TTL-compatible * Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and 32-pin LCC * Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT71256 is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT's highperformance, high-reliability CMOS technology. Address access times as fast as 20ns are available with power consumption of only 350mW (typ.). The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a low-power standby mode as long as CS remains HIGH. In the full standby mode, the low-power device consumes less than 15W, typically. This capability provides significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability where the circuit typically consumes only 5W when operating off a 2V battery. The lDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600 mil) plastic DIP, and 32-pin LCC providing high board-level packing densities. The IDT71256 military RAM is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0 ADDRESS DECODER A14 262,144 BIT MEMORY ARRAY
V CC GND
I/O 0 INPUT DATA CIRCUIT I/O 7 I/O CONTROL
CS OE WE
CONTROL CIRCUIT
2946 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-2946/7
7.2
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IDT71256 S/L CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
D28-3 P28-1 P28-2 D28-1 SO28-5
23 22 21 20 19 18 17 16 15
V CC WE A13 A8 A9 A11 OE A10 CS I/O 7 I/O 6 I/O 5 I/O 4 I/O 3
TRUTH TABLE(1)
WE
X X H H L
CS
H VHC L L L
OE
X X H L X
I/O High-Z High-Z High-Z DOUT DIN
Function Standby (ISB) Standby (ISB1) Output Disabled Read Data Write Data
2946 tbl 02
NOTE: 1. H = VIH, L = VIL, X = Don't Care
2946 drw 02
DIP/SOJ TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Com'l. Mil. -0.5 to +7.0 Unit V Terminal Voltage -0.5 to +7.0 with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current 0 to +70 -55 to +125 -55 to +125 1.0 50
A7 A 12 A14 NC VCC
WE
INDEX
A13
TA TBIAS
A8 A9 A11 NC A10
-55 to +125 -65 to +135 -65 to +150 1.0 50
C C C W mA
4
3
2
A6 A5 A4 A3 A2 A1 A0 NC I/O0
5 6 7 8 9 10 11 12
1
32 31 30 29 28 27 26 25 24 23 22
TSTG PT IOUT
L32-1
OE
21 13 14 15 16 17 18 19 20
I/O7 I/O6
CS
2946 drw 03
NOTE: 2946 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PIN DESCRIPTIONS
Name A0-A14 I/O0-I/O7 Addresses Data Input/Output Chip Select Write Enable Output Enable Ground Power
2946 tbl 01
I/O 1 I/O 2 GND NC I/O 3 I/O 4 I/O 5
32-Pin LCC TOP VIEW
Description
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Max. Unit 11 11 pF pF
CS WE OE
GND VCC
NOTE: 2946 tbl 04 1. This parameter is determined by device characterization, but is not production tested.
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IDT71256S/L CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Commercial Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5.0V 10% 5.0V 10%
2946 tbl 05
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0 -- --
Max. Unit 5.5 0 6.0 0.8 V V V V
NOTE: 2946 tbl 06 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS(1, 2)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71256S/L20 Symbol ICC Parameter Dynamic Operating Current CS VIL, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS VHC, VCC = Max., f = 0 Power Com'l. S L S L S L -- 135 -- 3 -- 0.4 Mil. -- -- -- -- -- -- 71256S/L25 Com'l. -- 115 -- 3 -- 0.4 Mil. 150 130 20 3 20 1.5 71256S/L30 Com'l. -- -- -- -- -- -- Mil. 145 125 20 3 20 1.5 71256S/L35 Com'l. -- 105 -- 3 -- 0.4 Mil. 140 120 20 3 20 1.5 mA mA Unit mA
ISB
ISB1
71256S/L45 Symbol ICC Parameter Dynamic Operating Current CS VIL, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS VHC, VCC = Max., f = 0
71256S/L55
71256S/L70 Com'l. -- -- -- -- -- --
71256S/L85(3) 71256S/L100(3) Mil. 135 115 20 3 20 1.5
2946 tbl 07
Power Com'l. Mil. Com'l. Mil. S L S L S L -- 100 -- 3 -- 0.4 135 115 20 3 20 1.5 -- -- -- -- -- -- 135 115 20 3 20 1.5
Mil. Com'l. Mil. Com'l. 135 115 20 3 20 1.5 -- -- -- -- -- -- 135 115 20 3 20 1.5 -- -- -- -- -- --
Unit mA
ISB
mA
ISB1
mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC, all address inputs cycling at fMAX; f = 0 means no address pins are cycling. 3. Also available: 120 and 150 ns military devices.
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IDT71256 S/L CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2946 tbl 08
5V 480 DATAOUT 255 30pF*
DATAOUT 255
5V 480
5pF*
2946 drw 04
2946 drw 05
Figure 1. AC Test Load
Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ) *Includes scope and jig capacitances
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V 10%
IDT71256S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOL = 10mA, VCC = Min. VOH Output High Voltage IOH = -4mA, VCC = Min. -- 2.4 MIL. COM'L. MIL. COM'L. Min. -- -- -- -- Typ. -- -- -- -- -- -- -- Max. 10 5 10 5 0.4 0.5 -- IDT71256L Min. -- -- -- -- -- -- 2.4 Typ. -- -- -- -- -- -- -- Max. 5 2 5 2 0.4 0.5 -- V
2946 tbl 09
Unit A A V
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Typ. (1) VCC @ Symbol VDR ICCDR tCDR tR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition -- MIL. COM'L. Min. 2.0 -- -- 0 tRC(2) 2.0v -- -- -- -- -- 3.0V -- -- -- -- -- 2.0V -- 500 120 -- -- Max. VCC @ 3.0V -- 800 200 -- -- Unit V A ns ns
2946 tbl 10
CS VHC
NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed, but not tested.
7.2
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IDT71256S/L CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE VDR2V VIH VDR VIH
2946 drw 06
VCC tCDR CS
4.5V
4.5V tR
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
71256L20 Symbol Read Cycle tRC tAA tACS tCLZ
(2) (2) (1)
71256S25 71256L25 Min. Max.
71256S30(3) 71256L30(3) Min. Max.
71256S35 71256L35 Min. Max.
71256S45 71256L45 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid
(2) (2)
20 -- -- 5 -- -- 2 2 5
-- 20 20 -- 10 10 -- 8 --
25 -- -- 5 -- -- 2 2 5
-- 25 25 -- 11 11 -- 10 --
30 -- -- 5 -- -- 2 2 5
-- 30 30 -- 15 13 -- 12 --
35 -- -- 5 -- -- 2 2 5
-- 35 35 -- 15 15 -- 15 --
45 -- -- 5 -- -- 0 -- 5
-- 45 45 -- 20 20 -- 20 --
ns ns ns ns ns ns ns ns ns
tCHZ tOE tOLZ
Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change
tOHZ tOH
Write Cycle tWC tCW tAW tAS tWP tWR tDW tWHZ tDH tOW
(2) (2)
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Write Enable to Output in High-Z Data Hold from Write Time Output Active from End-of-Write
20 15 15 0 15 0 11 -- 0 5
-- -- -- -- -- -- -- 10 -- --
25 20 20 0 20 0
13
-- -- -- -- -- -- -- 11 -- --
30 25 25 0 25 0 14 -- 0 5
-- -- -- -- -- -- -- 15 -- --
35 30 30 0 30 0 15 -- 0 5
-- -- -- -- -- -- -- 15 -- --
45 40 40 0 35 0 20 -- 0 5
-- -- -- -- -- -- -- 20 -- --
ns ns ns ns ns ns ns ns ns ns
2946 tbl 11
-- 0 5
NOTES: 1. 0 to +70C temperature range only. 2. This parameter guaranteed by device characterization, but is not production tested. 3. -55 to +125C temperature range only.
7.2
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IDT71256 S/L CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
71256S55(1) 71256L55(1) Symbol Read Cycle tRC tAA tACS tCLZ(2) tCHZ tOE tOLZ
(2) (2) (2)
71256S70(1) 71256L70(1) Min. Max.
71256S85(1) 71256L85(1) Min. Max.
71256S100(1,3) 71256L100(1,3) Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select Access Time Chip Deselect to Output in Low-Z Output Enable to Output in Low-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change
55 -- -- 5 -- -- 0 0 5
-- 55 55 -- 25 25 -- 25 --
70 -- -- 5 -- -- 0 0 5
-- 70 70 -- 30 30 -- 30 --
85 -- -- 5 -- -- 0 -- 5
-- 85 85 -- 35 35 -- 35 --
100 -- -- 5 -- -- 0 -- 5
-- 100 100 -- 40 40 -- 40 --
ns ns ns ns ns ns ns ns ns
tOHZ tOH
Write Cycle tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW
(2)
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from Write Time (WE) Write Enable to Output in High-Z Output Active from End-of-Write
55 50 50 0 40 0 25 0 -- 5
-- -- -- -- -- -- -- -- 25 --
70 60 60 0 45 0 30 0 -- 5
-- -- -- -- -- -- -- -- 30 --
85 70 70 0 50 0 35 0 -- 5
-- -- -- -- -- -- -- -- 35 --
100 80 80 0 55 0 40 0 -- 5
-- -- -- -- -- -- -- -- 40 --
ns ns ns ns ns ns ns ns ns ns
2946 tbl 11
(2)
NOTES: 1. -55C to +125C temperature range only. 2. This parameter guaranteed by device characterization, but is not production tested. 3. Also available: 120 and 150 ns military devices.
7.2
6
IDT71256S/L CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA tOH
OE
tOE tOLZ
(5)
tOHZ
(5)
CS
tACS tCLZ DATA OUT
2946 drw 07
(5)
tCHZ
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC ADDRESS tAA tOH DATA OUT
2946 drw 08
tOH
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
tACS tCLZ (5) DATA OUT
2946 drw 09
tCHZ
(5)
NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
7.2
7
IDT71256 S/L CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 5, 7) WE
tWC ADDRESS tOHZ
(6)
OE
tAW
CS
tAS tWP
(7)
tWR
WE
tWHZ DATA OUT
(4) (6)
tOW
(4)
tDW DATA IN
tDH
2946 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 5) CS
tWC ADDRESS tAW
CS
tAS tCW (7) ttWR
WE
tDW DATA IN
2946 drw 11
tDH2
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
7.2
8
IDT71256S/L CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT 71256 Device Type X Power XXX Speed XXX Package X Process/ Temperature Range Blank B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B
TD D Y P L
300 mil CERDIP (D28-3) 600 mil CERDIP (D28-1) 300 mil SOJ (SO28-5) 600 mil Plastic DIP (P28-1) Leadless Chip Carrier (32-pin) (L32-1)
20 25 30 35 45 55 70 85 100 120 150
Commercial Only Military Only Military Only Military Only Military Only Military Only Military Only Military Only
Speed in nanoseconds
S L
Standard Power Low Power
2946 drw 12
7.2
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